(1) Field of the Invention:
The present invention relates to a method of testing LSIs and, more particularly, to an acceleration testing of the reliability of LSIs.
(2) Description of the related art:
An acceleration testing of the reliability of an LSI (hereinafter simply referred to as "acceleration testing") has for its purpose to cause early generation of an initial failure (i.e., fault) of an LSI by holding the LSI, under application of a high voltage (of 6 V, for instance, if the normal operation voltage of the LSI is 5 V), exposed to a high temperature environment for a long time. This high voltage and high temperature environment is referred to as an acceleration test environment. If a fault occurs in the acceleration test environment, it can be detected in a short period of time after the completion of the acceleration test by means of an LSI tester with the LSI being held in the normal environment.
Troubles may be classified into several types. In connection with the acceleration test, restorable faults and non-restorable faults are considered here. A restorable fault is reproducible only in a specific environment such as the acceleration test environment noted above. A non-restorable fault, occurring once, for instance, such fault as a breaking of wirings is reproducible not only in the environment noted above but also in a restored normal temperature environment.
For the acceleration test, a burn-in furnace is used, which is capable of controlling the setting of the acceleration test environment noted above. As the acceleration test, there are following three different kinds of tests with different operations of the LSI to be tested placed in the burn-in furnace:
Acceleration test (1), in which only a source voltage is supplied to the LSI under test;
Acceleration test (2), in which a source voltage and a clock signal are supplied to the LSI under test; and
Acceleration test (3), in which other signals in addition to the source voltage and the clock signal are supplied to the LSI under test to operate the LSI as much as possible for the test.
The test (1) aims at an early generation of the non-restorable fault. In this test, however, it is impossible to control the internal gate states of the LSI under test because only a source voltage is supplied thereto. In other words, in this test the LSI under test does not operate logically. Therefore, the internal gates of the LSI are not activated (i.e., not inverted from "1" to "0" or from "0" to "1"). For example, therefore, if there is no potential difference between both the ends of a wiring which is about to be broken, no change in state occurs, and it is impossible to generate a fault of breaking of the wiring, which is a non-restorable fault.
The test (2) is one step ahead of the above test (1). In this test, a clock signal is also supplied to the LSI under test. Thus, a wiring for the clock signal and gates which receive directly the clock signal are activated to undergo equivalently normal operation, thus permitting the generation of a non-restorable fault at the above limited parts or components. However, a majority of gates are not activated and, therefore, the detection percentage is still low.
The test (3) aims at generating non-restorable faults in all internal parts of the LSI under test by activatedly operating a majority of gates in the LSI as in the normal operation. In one conceivable method of carrying out the test (3), applied to the testing of such an active LSI as a microprocessor, for operating the microprocessor or the like under test, a simple test system is produced using a memory and a TTL or like IC-LSI for memory access controlling. The whole test system is then set in a burn-in furnace and is operated by externally supplying to it a source voltage, a clock signal, a reset signal, etc. Thus, a majority of gates in the LSI under test are activated as in the normal operation to cause generation of non-restorable faults latent in all internal parts of the LSI. The test (3) is carried out similarly for testing a passive LSI such as a peripheral LSI for a microprocessor.
In another method of carrying out the test (3), a test like a selection test is carried out continuously on an LSI under the acceleration test environment by using an LSI tester.
As shown above, the prior art acceleration tests (1) and (2) are incapable of activating all the internal gates of the LSI under test and, therefore, provide for only low percentages of generation and detection of non-restorable faults.
The acceleration test (3) in the method of externally controlling a special test system containing an LSI under test, the system being set in a burn-in furnace, is not feasible because it is necessary to guarantee that the IC-LSI and other associated parts constituting the test system other than the LSI under test operate normally even under the acceleration test environment noted above and also because it is necessary to load programs in the memory of the test system from the outside of the burn-in furnace.
The method of carrying out the acceleration test (3) by using an LSI tester is nearly an ideal method. However, in this method an expensive LSI tester has to be used exclusively for long time (i.e., several to several ten hours for one acceleration test). In addition, the number of LSIs that can be tested simultaneously in one acceleration test is limited. Therefore, this method requires very high cost for conducting test.